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Altera_Forum
Honored Contributor
7 years agoDear Mr. Anand
I am sorry. I can't share any files because of our company policy. But I add pseudo code. build.bat is changed only cpp filename and -ghdl option for test-fpga. # include <> ... typedef ac_fixed<8,8,false> fixed8; typedef ac_fixed<1,1,false> fixed1; typedef ac_fixed<10,10,false> fixed10; component void func(stream_in<fixed8> a, stream_in<fixed1> b, stream_out<fixed10> c) { hls_init_on_reset static fixed8 d[xx]; hls_init_on_reset static fixed1 e[xx]; for (){ // Non blocking read1 bool success = false; fixed8 data = a.tryRead(success); if (success) { //Shift register # pragma unroll for ... d[] = data; } // Non blocking read2 bool success1 = false; fixed8 data1 = b.tryRead(success1); if (success1) { //Shift register # pragma unroll for ... e[] = data1; } //--------------- The following makes error ---------------- fixed10 m = d[] *e[]; ... c.write(out); } } int main() { //Generate stream in data and buffer // Invoke component return 0; } That's all. What can I do?