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Altera_Forum's avatar
Altera_Forum
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16 years ago

VoIP (AN374) questions

Hi all,

1) Firstly, I worked on a 3C40 FPGA devboard with a 1Gbe Marvell 88E1119R PHY.

At this time, I have a fully functionnal uClinux + Boa webserver system using Opencores 10/100 MAC, as described in this simple scheme :

http://img260.imageshack.us/img260/192/uclinuxopencoresmac.png

uClinux runs from the SDRAM memory and the Flash memory includes bootloader + JFFS2 file system....

2) Now, I want to add to this working design the Vider Over IP (AN374) block but only the Transmitter path, as described in this second scheme :

http://img191.imageshack.us/img191/5223/voipuclinuxtsemac.png

I have several high-level questions about this design :

+ Is it possible to use sdram controller instead of ddr sdram controller for the RTP transmitter buffering ?? I think here about latency issues...

+ If YES, is it possible to "share" the sdram between the uClinux system and the RTP transmitter ??

+ Is it possible to use the altera tse mac in the same time with uclinux (LAN --> webserver and webserver --> LAN) and with the data path (RTP + UDP/IP --> LAN) ??? What happened if uClinux and UDP/IP block sends data simultaneously to the MAC ???

Thanks for your precious help guys !!!

Papy

11 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    hello guys.........

    i just have the an374 working with a uclinux cpu with boa server to configure the an374..........is finished and working

    i had some problems like you

    --- Quote Start ---

    The video appears but with a high degree of artefacts (green square all over the screen) and when I check the statistics, the number of corrupted packets is very elevated !!

    --- Quote End ---

    try look your ts packet size 188 or 204 .....you need detect and if change you need reset the ts input buffer......

    monitore the signal named ts_valid[0] and ts_data at ts input buffer in signal tap

    good luck

    Franz Wagner