verilog example of a dual port ram with a burst capable avalon interface ??

Hi,

Refer the below links,Which gives information for single port ram which may help.

https://www.altera.com/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-avalon-mm.html

https://www.altera.com/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-avalon-memory-slave.html

http://alterawiki.com/wiki/interfacing_to_altera_external_memory_controller_ip

Yes, you can create a template/design.

Referftp://ftp.altera.com/up/pub/altera_material/14.0/tutorials/making_qsys_components.pdf

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)

--- Quote Start ---

Hi,

Refer the below links,Which gives information for single port ram which may help.

https://www.altera.com/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-avalon-mm.html

https://www.altera.com/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-avalon-memory-slave.html

http://alterawiki.com/wiki/interfacing_to_altera_external_memory_controller_ip

Yes, you can create a template/design.

Referftp://ftp.altera.com/up/pub/altera_material/14.0/tutorials/making_qsys_components.pdf

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)

--- Quote End ---

first url link: it has a master template

second url link: it has a slave template but not burst capable

third link: out of scope.

pdf Link:

Creating a template means , In vivado, tool generates axi4-full slave top wrapper with all the logic built into it like it takes care of burst type, internal address increments (burst) and necessary response and acknowledgement handling and even a small portion of dpram under userlogic section. The pdf you provided implements a single register that too no involvement of READ signal. I am looking for a more advanced code with a burst capable.

For understanding sake , i am asking a dualport ram verilog code surrounded by a avalon interface logic. I want to study it and tag this into my platform designer and finally want to do burst read and write testing through simple DMA Controller. :(

Thanks,

Anil