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Altera_Forum
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14 years ago

Verilog - minimizing logic

Hi I'm generating some asymmetric waveforms from a counter, and am able to adjust the counts where it changes output. Hence I'd like to choose numbers that utilize the minimum amount of logic ...
Altera_Forum's avatar
Altera_Forum
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14 years ago

ISTR that somewhere you can see a logic diagram (or similar) after one stage of the syntheses. But the actual logic used can depend on timing (and other) constraints.

I'd guess that you'd be better counting down to zero (or until carry) and reloading the counter with a sequence of values.