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Altera_Forum
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14 years ago

Verilog - minimizing logic

Hi I'm generating some asymmetric waveforms from a counter, and am able to adjust the counts where it changes output. Hence I'd like to choose numbers that utilize the minimum amount of logic ...
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Altera_Forum
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14 years ago

This kind of compare logic is minimized if you choose numbers which allow comparision of a limited number of bits.

This can be easily evaluated from the binary representation of you numbers,

e.g (Counter1 >= 128) && (Counter1 < 176) is efficient because only 3 upper bits need to be compared in order to evaluate the expression.

While (Counter1 >= 135) && (Counter1 < 182) would require far more complex logic.