Verify Failed in Nios II

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Hmmm couldn't find it on the web. Ok, the issue I was referring to only occurs in 9.0 with the new "Altera ALTPLL" component that was introduced in 9.0 The issue will be resolved in the next version of the tools but essentially the Avalon-MM slave port of the PLL had it's reset line wired directly into the PLL areset port. So if you filtered reset_n from outside the system with the PLL locked signal you have a reset loop and you'll get stuck. I only added this to the post just in case others run into it, I don't think you ran into this otherwise your system would have never worked.

i thought of another thing that could cause issues. if you are using a cyclone/stratix ii or earlier nios development kit, make sure the reconfig_request_n signal is either pulled high, or that pin is set to input tristate (there is a pullup on that line). The board user documentation explains what that signal is for so I won't go into the details of the failure that will occur. By default Quartus II will set unused signals to ground on the older device families so if you didn't connect reconfig_request_n in your design, it would get pulled low by default..... which means you .sof would get overwritten as soon as the design comes up live. If you ran into this chances are by the time you go to download your software you are using the factory or user hardware that's programmed into flash.

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I am new in Nios and I am running the following an excellent step-by-step tutorial at:

https://www.badprog.com/electronics-quartus-ii-creating-your-first-sopc-with-qsys-and-nios-ii-software

But, different from DE1 board used in the tutorial, I am using an old'2004 EP60F672C5ES Nios Stratix II Development Kit. The tutorial was adapted by me to be used on my board by the assignment of Stratix ii pins instead of the DE1 ones. After this, all steps were executed perfectly, except for the last one, which is the the download of the .elf code to the board. It generates a "verify failed" message. And my primary suspect is the setting of the signal cited by BadOmen.

Sorry about the basic questions, but:

1. How can I check the status of the reconfig_req_n?

2. How can I set this in Verilog?