Verified OK - Leaving target processor paused

This could be a pin assignment issue. Ensure that clk and reset are connected to the respective pins in the board.

For DE4, I found that assigning clk to pin OSC_50_B7 (50 Mhz clk input for Bank 7c 1.8v pin A19) worked.

Also, I think the frequency of clk input from board must match frequency in SOPC builder (50MHz usually) unless you are using an exclusive PLL