Honored Contributor
Honored ContributorThe Hardware which i am using is provided by Altera, and code which i am using is modified version of simple_socket_server example,
i have add only sync_detector which extract synchronous word from serial bit stream and start generating load pulse at every 8-bit (conversion time from serial to 8 bit parallel data). so that at every pulse this 8-bot data to be read and store in FPGA memory as this load pulse (interrupt ) comes at every 125 kbps which IIC not able to handle (it misses most of the interrupt) so i switch to VIC. in my previous project i am comfortable use the VIC and have not face any problem like this. I am using altera ESDK board (Cyclone-III) my application is like this Image data (TCP) PC---->ESDK-RX---------Serial Synchrionous Data @ 1 mbps------>(Sync Detect)-->ESDK-Tx------>PC (Received Image Data through TCP) |-------------------------------Project-I----------------------------->|<----------------------Project-II------------------------->| Rather i am using my previous project hardware for development of new project Regards
