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Altera_Forum
Honored Contributor
12 years agoThanking you for your post
1. I am using SOPC 2. ddr2_bot_auxfull = 165.0 Mhz 3. ddr2_bot_auxfull = 165.0 Mhz 4. ddr2_bot_auxhalf = 82.5 5. I haven’t give any time constraints though Quartus generate message like critical warning: timing requirement not met 6. I just modified the simple socket server example for my requirement like taking data on every interrupt from external pin of nios and store it and also acknowledge received interrupt on external pin temp_out 7. Regarding preemption I haven’t any knowledge but I think this can be use when multiple interrupt use same shadow register. 8. I have 7 shadow register set and VIC can handle 9 interrupt regards Kaushal