USING SIGNAL TAP TO MONOTOR AVALON_BUS WITH NIOS DESIGN

Hi aiedb​ ,

This usually comes down to a few common issues when using SignalTap on Avalon-MM in a Nios II / Platform Designer system:

1. Wrong signal location (very common)

Make sure you’re tapping the signals at the correct hierarchy. Avalon signals go through the interconnect, so if you tap near the IP but not the actual connected interface, you may see nothing.

2. Signal optimization

Quartus might optimize away unused signals. Try setting the signals or module to preserve/keep, or enable SignalTap node preservation during compilation.

3. Clock mismatch

Double check that SignalTap is clocked by the same clock domain as the Avalon interface to the on-chip flash. If the clock is wrong, triggers won’t fire.

4. Trigger condition too strict

A rising edge on write may not trigger as expected (due to pipelining or waitrequest).

Try:

Trigger on write == 1

Or (write && chipselect)

Or even immediate trigger just to confirm activity

5. Transaction may not be happening

Confirm your software is actually performing the write to CFM0. You can temporarily add a simple debug (e.g. GPIO toggle) to correlate.

6. Capture depth

Increase SignalTap buffer depth—short Avalon transactions can be easy to miss.

7. Recompile properly

Make sure you did a full recompile after adding SignalTap and programmed the correct .sof.