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1) Make sure the EPCS pins are configured to be used as general purpose I/O in the Quartus device settings. Otherwise the fpga can properly load the hardware configuration but then the pins are not accessible by Nios or any other 'soft' device.
2) Sure you can run Nios at 100MHz (or whatever f you need) and keep EPCS at 25MHz: this is a quite common configuration.
You simply need a PLL to generate the 2 clocks and a clock crossing bridge between the two sections in Qsys.
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Thanks for the quick reply.
I am struggling with your first suggestion - If I open up quartus, and go Assignments->Device then Device and Pin Options.
There seems no where I can set general purpose I/O - on dual purpose pins I only get offered Data 15..8 and Data 7..5 - not the EPCQ pins.
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