Using 2 timers ?

Are you sure your timer is running?

I think you must write this to control register: IOWR(TIMER_500M_IRQ, 1, 7)

We have made the test with : IOWR(TIMER_500M_IRQ, 1, 7)

but only the first timer is working,

Thank you.

With 'not working' do you mean the timer irq handler function is not called or did you actually check timer is not running at all?

Is the 500ms period fixed or programmable?

Ialso suggest you use this one to control the timer:

IOWR_ALTERA_AVALON_TIMER_CONTROL(TIMER_500M_IRQ,

ALTERA_AVALON_TIMER_CONTROL_CONT_MSK

| ALTERA_AVALON_TIMER_CONTROL_START_MSK

| ALTERA_AVALON_TIMER_CONTROL_ITO_MSK);

which is more portable.

Thank you Cris72.

For the moment, I don't know if the 200ms timer is working or not working or if his timer irq handler function is called or not called. But we note that it don't go in 200ms timer irq handler function. The 500ms timer irq handler function works correctly.

The values of the timers are defined in SOPC builder.

We make the test with your code.

We make a test with this type of syntax for configuring each timers :

IOWR_ALTERA_AVALON_TIMER_CONTROL(TIMER_500M_IRQ,

ALTERA_AVALON_TIMER_CONTROL_CONT_MSK

| ALTERA_AVALON_TIMER_CONTROL_START_MSK

| ALTERA_AVALON_TIMER_CONTROL_ITO_MSK);

But it doesn't work.

Thank you.

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The values of the timers are defined in SOPC builder.

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Did you set the option for programmable period in sopc builder?

In case, read and check the periodl/periodh registers.

Anyway, as I said before, you must make sure the timer is running.

You can't expect an idle timer to generate IRQs.

For a new test, we have declared the second timer in SOPC builder in customer mode with writable/readable period, writable/readable control and writable/readable snap.

This timer works fine if it is declared as system clock timer otherwise it doesn’t work. We also try to read the timer period and the snap value, in the both case the read values was wrong (-1).

(Before the snap reading we make a snap writing to update the values on the registers, like it is explained in the timer datasheet)

example of our code :

// declaration of the 250ms timer

IOWR_ALTERA_AVALON_TIMER_PERIODL(TIMER_250M_IRQ, 0x0900);

IOWR_ALTERA_AVALON_TIMER_PERIODH(TIMER_250M_IRQ, 0x003D);

alt_irq_enable(TIMER_250M_IRQ);

IOWR_ALTERA_AVALON_TIMER_CONTROL(TIMER_250M_IRQ, ALTERA_AVALON_TIMER_CONTROL_CONT_MSK | ALTERA_AVALON_TIMER_CONTROL_START_MSK | ALTERA_AVALON_TIMER_CONTROL_ITO_MSK);

alt_irq_register( TIMER_250M_IRQ, NULL, TIMER250M_IRQ);

// reading of the programmable period

periodl=IORD(TIMER_250M_IRQ, ALTERA_AVALON_TIMER_PERIODL_REG);

periodh=IORD(TIMER_250M_IRQ, ALTERA_AVALON_TIMER_PERIODH_REG);

// reading with the snapshot (writing and then reading)

IOWR_ALTERA_AVALON_TIMER_SNAPL(TIMER_250M_IRQ, 0x00);

IOWR_ALTERA_AVALON_TIMER_SNAPH(TIMER_250M_IRQ, 0x00);

periodl=IORD_ALTERA_AVALON_TIMER_SNAPL(TIMER_250M_IRQ);

periodh=IORD_ALTERA_AVALON_TIMER_SNAPH(TIMER_250M_IRQ);

At this moment, we develop a new solution with a single timer. In this timer, we use a counter to have the second timer period.

We think that we give up the solution with 2 timers.

Thank you Cris72 for your help.

I do use 2 timers in the same way you do. I even used 3 in a project.

So, there's definitely no problem with the timer itself. It MUST work.

Please, perform a few more tests before giving up.

- register the irq before starting the timer

- remove alt_irq_enable; this is not required

- disable and reset the timer first of all, before programming period:

IOWR_ALTERA_AVALON_TIMER_CONTROL(TIMER_250M_IRQ, 0)

- try without enabling irq and make sure the timer runs; in other words, remove alt_irq_register() and read snap registers as you already do

Remark: writing both snap registers is not necessary; writing just one of them is enough to latch both.

We have tried your solution unfortunately it’s the same problem. Only one timer works and we can’t read the period programmed and the snapshot value. Both interval timer are declared as custom timer on SOPC Builder.

Here the code for the 500ms timer (same code for 250ms) :

// declaration of the 500ms timer

IOWR_ALTERA_AVALON_TIMER_CONTROL(TIMER_500M_IRQ, 0);

IOWR_ALTERA_AVALON_TIMER_PERIODL(TIMER_500M_IRQ, 0x9680);

IOWR_ALTERA_AVALON_TIMER_PERIODH(TIMER_500M_IRQ, 0x0098);

alt_irq_register( TIMER_500M_IRQ, NULL, TIMER500M_IRQ);

IOWR_ALTERA_AVALON_TIMER_CONTROL(TIMER_500M_IRQ, ALTERA_AVALON_TIMER_CONTROL_CONT_MSK | ALTERA_AVALON_TIMER_CONTROL_START_MSK | ALTERA_AVALON_TIMER_CONTROL_ITO_MSK);

// reading with the snapshot

IOWR_ALTERA_AVALON_TIMER_SNAPL(TIMER_500M_IRQ, 0x00);

periodl=IORD_ALTERA_AVALON_TIMER_SNAPL(TIMER_500M_IRQ);

periodh=IORD_ALTERA_AVALON_TIMER_SNAPH(TIMER_500M_IRQ);

Do you have a code example ?

Thanks

My code sample is the same of yours, except the different timer name.

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Only one timer works and we can’t read the period programmed

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Even if timer doesn't work, you should be able to read back the programmed period.

This is very strange: timer is one of the simplest devices, very easy to work with.

Are you sure there is no timing issues in fpga configurations? Is your design correctly constrained?