user logic peripheral

Adrian,

Saying "have to read twice" is a hint to your problem. Here's what's going on: You are only updating the readdata bus on positive clock edges. Internal to the Avalon bus the chipselect signal is driven by combinational logic driven by the readaddress, such that CS is asserted after a clock edge. By default, your user peripheral will have zero for read latency. Avalon will sample readdata on the first clock edge after CS, but you update readdata AFTER the clock edge. If you read twice, you are actually reading what you drove on readdata for the previous read. You'll notice that everything will be delayed by one read. See the Avalon bus manual for descriptions of the bus cycle timings.

You can fix by 1) setting read latency to one in your .PTF (or maybe in SOPC Builder, can't remember) or making your read logic asynchronous: (I'm a VHDL guy so pardon any syntax errors) Note that readdata only depends on address, not write_n!

always @(address)
begin
  case(address)
   3'b000 : readregister = width;
   3'b001 : readregister = period;
   3'b010 : readregister = divider;
   3'b011 : readregister = ~width;
   default : readregister = 32'b10001111000010100000000000001010;
  endcase
 end

-Tim