user logic peripheral

Hello Adrian,

Without loading your system and trying it myself it difficult to say for sure what the problem is. Your assumption on the IO<Write and Read> macros is correct. So you may want to take the approach of ruling out hardware first.

Taking quick look at your hdl, because you are having problems there looks like there are somethings you might want to consider modifing in the spirit of being cautious.

1. In your always block for the write case and the read case logic you are using a mix of both non-blocking and blocking assignments. In general, for sync logic, you proably want to use a non-blocking assignment( <= ). For example:

Rather than this

case(address)
   3'b000 : readregister = width;
   3'b001 : readregister = period;
   3'b010 : readregister = divider;
   3'b011 : readregister = ~width;
   default : readregister = 32'b10001111000010100000000000001010;

Try this:

case(address)
   3&#39;b000 : readregister <= width;
   3&#39;b001 : readregister <= period;
   3&#39;b010 : readregister <= divider;
   3&#39;b011 : readregister <= ~width;
   default : readregister <= 32&#39;b10001111000010100000000000001010;

It would be interesting to know if this changes your behavior.

In addition, for your case statements you are not filling out all the cases. For example in the write case you don&#39;t give a default case and in addition for every possible case, you do not assign a value to every register.

Again being cautious, rather than this:

case(address)
   3&#39;b000 : width <= writedata;
   3&#39;b001 : period <= writedata;
   3&#39;b010 : divider <= writedata;
   default :;
  endcase

Try this:

case(address)
   3&#39;b000 : width <= writedata;
                 period <= period; 
                 divider <= divider; 
   3&#39;b001 : period <= writedata;
                 width <= width;
                 divider <= divider; 
.............etc........
   default :
               Do something here;
  endcase

Good Luck,

Altera

hbutler97