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Altera_Forum
Honored Contributor
Honored ContributorUnable to use Nios II/e?
I've been trying to instantiate a Nios II/e core with no success. I am using external SRAM, one 16 bit PIO, and a 50Mhz clock. I am able to synthesize the design, generate the sof file, and con...
Altera_ForumHonored Contributor
Honored ContributorAhhh sorry I mixed up the two. Is the CPU the only thing you change between the two designs? Is the project fully constrained and does it meet all timing requirements?
Is the JTAG module slave interface on the CPU connected to both the instruction and data masters? In some cases you need to add a pipeline bridge between those masters and the JTAG debug module in order to meet timing requirements.
