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Altera_Forum
Honored Contributor
15 years agoThe problem is that the current atse driver (besides many other assumptions) assumes that we will never use PCS mode. Here is the patch that should fix this problem. To compile it define USE_PCS_MODE. Ill try to submit it.
diff -uNr nios2-linux.vanilla/linux-2.6/drivers/net/atse.h nios2-linux/linux-2.6/drivers/net/atse.h
--- nios2-linux.vanilla/linux-2.6/drivers/net/atse.h 2010-06-02 15:42:18.000000000 -0500
+++ nios2-linux/linux-2.6/drivers/net/atse.h 2010-06-29 14:32:24.000000000 -0500
@@ -72,10 +72,18 @@
/* number of bytes in one MDIO register */
# define ATSE_PHY_ID_1_OFFSET (2 * BYTES_IN_WORD)
# define ATSE_PHY_ID_2_OFFSET (3 * BYTES_IN_WORD)
+
+#ifdef USE_PCS_MODE
+#define ATSE_MAC_REG_MDIO_ADDR_1 (ATSE_MAC_BASE + 0x3C )
+#define ATSE_MAC_REG_MDIO_ADDR_0 (ATSE_MAC_BASE + 0x40 )
+#define ATSE_MAC_REG_PCS_0 (ATSE_MAC_BASE + 0x0200)
+#define ATSE_MAC_REG_MDIO_SPACE_0 (ATSE_MAC_BASE + 0x0280)
+#else
# define ATSE_MAC_REG_MDIO_ADDR_0 (ATSE_MAC_BASE + 0x3C )
# define ATSE_MAC_REG_MDIO_ADDR_1 (ATSE_MAC_BASE + 0x40 )
# define ATSE_MAC_REG_MDIO_SPACE_0 (ATSE_MAC_BASE + 0x0200)
# define ATSE_MAC_REG_MDIO_SPACE_1 (ATSE_MAC_BASE + 0x0280)
+#endif
# define ATSE_SET_PHY_MDIO_CONTROL(n) writel((n), ATSE_MAC_REG_MDIO_SPACE_0)
# define ATSE_GET_PHY_MDIO_CONTROL() readl(ATSE_MAC_REG_MDIO_SPACE_0)