UART with FIFO Buffer

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originally posted by feiwu@Nov 23 2005, 01:19 PM

dear edmund,

could you give the file ,thanks you very much!

my email: wfeiwu@21cn.com

best regards,

feiwu

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I have finished designing the UART having with FIFO without FIFO mode.

the components/entities are as follows:

Reciver State Machines - 1.write cycle

2.read cycle

Receiver Shift Register, Receiver FIFO and data register

Transmitter State Machines - 1.Write cycle for Data register and FIFO + Read cycle

for Data

2.read cycle for FIFO

3.shifting data out

Transmitter FIFO and data register, Receiver shift register

Register Bank

Register select logic

and Baud rate generator

I need a clarification:

The Baud rate generator is generating a clock from the system clock.

I am using baud clock for

Transmitter shift register

and transmitter state machine 3 for shifting data out

rest all transmitter aoperation is on system clock i.e. TXFIFO uses single clock

In RX logic

baud clock is used for RXshift register to shift in the data and for the state machine that controls shifting in the data and writing to FIFO/data register

ie. RX state machine 1

the RXFIFO and receiver state machine controlling the read cycle work on system clock.

I need confirmation that ifthe way I am using baud clock and the system clock is correct?

regards