New Contributor
Super ContributorBuffer len of 64 means it'll get full when it holds 64 bytes of pending transmit or receive data. May be can try reduce the len (must be a power of two) to ensure that buffer always full before a call to read using fgetc. A call to read something will only block when the SW buffer full. The minimum len is two, one did not work.
New ContributorLet me explain you what is our application of UART serial communication. In our system there are two H/W boards Board 1 and Board 2. One board(Board 1) is receiving many bytes(8 to 10 lakhs bytes) from external device using serial uart port (in non-blocking mode). This Board1 is receiving from external world and it is receiving exactly what is being sent and there is no issue in this board receiving data from external device. Board 1 now has uart serial communication with Board 2 in the system where Board 1 need to send these (8 to 10 lakhs bytes) data to Board 2 through uart port. Board 1 is using cyclone II fpga and we are using quartus 6 tool and SOPC for developing platform while Board 2 has cyclone iv and we are using quartus 18.1 tool and platform designer to integrate nios and other IPs (like UART etc). We are seeing that if we keep delay of 5ms means usleep(5000) in our source code when we are transmitting data bytes(using IOWR for writing base address of UART and checking status bit if it is clear means if data is read then only writing again on base address) from Board 1 and we are using blocking uart port to receive data bytes in Board 2(without any delay) it takes 32 minutes(too high) to send and receive almost 3.9 lakhs data bytes.
if we do not keep any delay in source code of board 1 and transmit data then board 2 is able to receive approx 2.4 lakhs data bytes but after that it is getting stucked. There is not dropping of bytes for 2.4 lakhs data bytes but after approx 2.4 lakhs it is not receiving any data byte (at board 2). Board 1 is able to send full 3.9 lakhs and coming out from for loop, whereas board 2 is getting stucked and not coming out from for loop.
As per your previous advise i tried to reduce the buff length from 64 to 2 (in Board 2 source code) but i am not able to see any improvement and also seeing that even after changing and saving the altera_avalon_uart.h file it is not getting reflected in altera_avalon_uart.h file.
We are thinking to use flow control mechanism(RTS/CTS) in uart ip core and need clarification from you whether it can solve the issue explained here. Please give us reference document for using flow control in UART IP core.
Please let us know your suggestions to come out from this issue.
