Honored ContributorHello
We need to use UART com on our NIOS poject We are using cycloneV what should be the best qsys architecture in order , so to free the cpu so it can perform other task while the systm is receiveing data from uart Thank you very much Shalom
Honored ContributorUse a UART core with rx FIFO or use the Altera standard UART core with a DMA controller.
Honored ContributorHi Cris
Thanks for youtr reply you mean by "Altera standard UART core with a DMA controller" the Altera 16550 UART? If yes, I understand from the spec that only an HPS processor can interface with Altera 16550 UART DMA side The following is from the Altera 16550 UART spec "DMA Support The DMA interface (DMA_EXTRA) is disabled by default. It must be enabled in the IP to have the additional DMA_Handshaking_tx and DMA_Handshaking_rx interfaces. dma support is only availablewhen used with the hps dma controller. The HPS DMA controller has the required handshake signals to control DMA data transfers with the IP through the DMA_Handshaking_tx and DMA_Handshaking_rx interfaces. The DMA handshaking interfaces are connected to the HPS through the f2h DMA request lines." But our cyclone V does not support HPS unit . so the only way is to use a rx fifo . right ? Shalom
Honored ContributorI mean the UART core which comes for free with Qsys has no FIFO; then you may need to add a dma component to manage rx data if you want performance.
Other commercial UART cores usually have FIFOs or a build-in dma (like the 16550 you mentioned), but the way to interface to Nios depends on the core specifications; you must refer to the datasheet or an application note from the vendor.Honored ContributorCris
thanks you very much for the help ! Shalom
