Uart Baud Rate Drop

Hi Eric,

Thank you for your reply.

I'm actually using the spl and the u-boot image from the same compile (by using the commands "make all" and "make uboot") and both are loaded via DS-5 since the SD-card seems to fail.

How can I check on the L4 settings (except the ones I can set in Qsys) and the divisors? I guess it has to be somewhere in the spl / uboot src code but I've only found the settings in socfpga_common.h:

*
 * L4 OSC1 Timer 0
 */
/* This timer use eosc1 where the clock frequency is fixed
 * throughout any condition */# define CONFIG_SYS_TIMERBASE        SOCFPGA_OSC1TIMER0_ADDRESS
/* reload value when timer count to zero */# define TIMER_LOAD_VAL            0xFFFFFFFF
/* Timer info */# define CONFIG_SYS_HZ            1000
/* Clocks source frequency to timer */# if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)# define CONFIG_TIMER_CLOCK_KHZ        2400# else
/* Preloader and U-Boot need to know the clock source frequency from handoff*/# define CONFIG_TIMER_CLOCK_KHZ        (CONFIG_HPS_CLK_OSC1_HZ / 1000)# endif

The EOSC1 frequency is running on a 20MHz quartz (in comparison to the Development board where it is running at 25MHz).

EDIT:

While reading the pll_config.h file I found the following settings:

# ifndef _PRELOADER_PLL_CONFIG_H_# define _PRELOADER_PLL_CONFIG_H_
# define CONFIG_HPS_DBCTRL_STAYOSC1 (1)
# define CONFIG_HPS_MAINPLLGRP_VCO_DENOM (0)# define CONFIG_HPS_MAINPLLGRP_VCO_NUMER (59)# define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT (0)# define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT (0)# define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT (0)# define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT (511)# define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT (511)# define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT (11)# define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK (1)# define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK (1)# define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK (0)# define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK (0)# define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK (0)# define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK (1)# define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK (0)# define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP (1)# define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP (1)
# define CONFIG_HPS_PERPLLGRP_VCO_DENOM (0)# define CONFIG_HPS_PERPLLGRP_VCO_NUMER (49)# define CONFIG_HPS_PERPLLGRP_VCO_PSRC (0)# define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT (511)# define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT (511)# define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT (511)# define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT (4)# define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT (9)# define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT (511)# define CONFIG_HPS_PERPLLGRP_DIV_USBCLK (4)# define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK (4)# define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK (4)# define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK (4)# define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK (3124)# define CONFIG_HPS_PERPLLGRP_SRC_SDMMC (2)# define CONFIG_HPS_PERPLLGRP_SRC_NAND (2)# define CONFIG_HPS_PERPLLGRP_SRC_QSPI (1)
# define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (0)# define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (15)# define CONFIG_HPS_SDRPLLGRP_VCO_SSRC (0)# define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT (1)# define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE (0)# define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT (0)# define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE (0)# define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT (1)# define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE (4)# define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT (5)# define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE (0)
# define CONFIG_HPS_CLK_OSC1_HZ (20000000)# define CONFIG_HPS_CLK_OSC2_HZ (20000000)# define CONFIG_HPS_CLK_F2S_SDR_REF_HZ (0)# define CONFIG_HPS_CLK_F2S_PER_REF_HZ (0)# define CONFIG_HPS_CLK_MAINVCO_HZ (1200000000)# define CONFIG_HPS_CLK_PERVCO_HZ (1000000000)# define CONFIG_HPS_CLK_SDRVCO_HZ (320000000)# define CONFIG_HPS_CLK_EMAC0_HZ (1953125)# define CONFIG_HPS_CLK_EMAC1_HZ (1953125)# define CONFIG_HPS_CLK_USBCLK_HZ (6250000)# define CONFIG_HPS_CLK_NAND_HZ (50000000)# define CONFIG_HPS_CLK_SDMMC_HZ (200000000)# define CONFIG_HPS_CLK_QSPI_HZ (2343750)# define CONFIG_HPS_CLK_SPIM_HZ (6250000)# define CONFIG_HPS_CLK_CAN0_HZ (6250000)# define CONFIG_HPS_CLK_CAN1_HZ (6250000)# define CONFIG_HPS_CLK_GPIODB_HZ (32000)# define CONFIG_HPS_CLK_L4_MP_HZ (100000000)# define CONFIG_HPS_CLK_L4_SP_HZ (100000000)
# define CONFIG_HPS_ALTERAGRP_MPUCLK (1)# define CONFIG_HPS_ALTERAGRP_MAINCLK (3)# define CONFIG_HPS_ALTERAGRP_DBGATCLK (3)
# endif /* _PRELOADER_PLL_CONFIG_H_ */

Have you been referring to that?

Thanks again for your time, I really appreciate your help!

Regards

Stefan