U-boot on NIOS II in SDRAM

Hi Eric, thank you for trying to help me!

TL;DR: I'm still stuck in not finding the entry for u-boot's initial arch/nios/cpu/start.s code to jump in.

My specs:
SoC FPGA: Cyclone V 5CSEMA5F31C6N
Board: DE1 Rev D
IDE: Quartus 18.1 on Linux (Debian 10)

Meanwhile, I found several documents, most important I studied the "Nios II Processor Booting from Altera Serial Flash (EPCQ)" doc. I'm still trying to get U-Boot running on the before mentioned Nios II Setup (slightly modified). Trying to boot into u-boot's start.S, I understand that I'm about to implement the scenario: "Nios II processor application executes in place from EPCQ flash".

My Setup:
I added a "Serial Flash Controller II Intel FPGA IP" and named it "EPCQ". I configured it as "EPCQ256" according to the DE1 Board reference paper, I/O Mode "STANDARD".

As described in the same document, I connect "reset" and "debug_reset_request" to "reset" of the EPCQ. "data_master" and "instruction_master" go to "avl_mem" of the EPCQ. Only "data_master" connects to "avl_csr" of the EPCQ.

avl_mem shows a Base at 0x0600_0000 and IRQ 0, after executing the tcl scripts "Assign Base Addresses" and "Assign IRQs".

Memory Map in QSYS
sdram.s1 0x0000_0000 - 0x03ff_ffff
epcq.avl_mem 0x0600_0000 - 0x07ff_ffff 0x0600_0000 - 0x07ff_ffff
sram.s1 0x0800_0000 - 0x0803_ffff
nios2.debug_mem_slave 0x0804_0800 - 0x0804_0fff 0x0804_0800 - 0x0804_0fff
epcq.avl_csr 0x0804_1000 - 0x0804_103f
led.s1 0x0804_1040 - 0x0804_104f
sw.s1 0x0804_1050 - 0x0804_105f
jtag_uart.avalon_jtag_slave 0x0804_1060 - 0x0804_1067

NB: sram - I call my on-chip memory sram

In my Nios II IP, on the "vector" menu tab I set reset vector to EPCQ.avl_mem. I entered the "Reset Vector Offset" to 0x00080000. I calculate the following:

minimum reset vector offset = .sof image start adddress + .sof image size) = 0x0 + 0x00080000 = 0x00080000

My resulting reset vector then becomes 0x06080000.

size = 0x00080000 - I went by the same document's example and did a mere guess! At smaller sizes QSYS showed overlapping errors, larger sizes gave "too large" errors.

I saved everything, generated QSYS and built my setup in Quartus. I opened a shell went to the Quartus project directory and there executed
$ java -jar ./sopc2dts.jar --force-altr -i ./linux_hw.sopcinfo -o linux_hw.dts. I copied the .dts file into the u-boot sources and registered it under menuconfig. My menuconfig .config was based on the cyclone IV example of the 10m50 board in u-boot.

In the meanwhile I programmed the DE1 board using the quartus programmer. I did neither specifically add a EPCQ device in the quartus programmer, nor generate a .jic nor a .hex for that. I guess u-boot should be able to deal with all that internally.

In the u-boot sources, then I edited the include/configs/linux_hw.h, adjustments I did:
// epcq
#define CONFIG_SYS_SDRAM_BASE 0xc6000000
#define CONFIG_SYS_SDRAM_SIZE 0x02000000

#define CONFIG_SYS_MONITOR_LEN 0x00080000

#define CONFIG_SYS_MONITOR_BASE ???

Here I thought of using the 0x06080000 or 0xc6080000 as reset / start point for CONFIG_SYS_MONITOR_BASE. U-boot does some computation which leads to a adress which for sure does not work out (am I doing something wrong?). In all cases "validation failed" at some addresses. I tried several addresses, all with and without |0xc0000000.

$ nios2-download -g u-boot
Using cable "DE-SoC [1-4.2.1]", device 2, instance 0x00
Processor is already paused
Initializing CPU cache (if present)
OK
Downloaded 263KB in 0.9s (292.2KB/s)
Verifying C6000000 ( 0%)
Verify failed between address 0xC6000000 and 0xC600FFFF
Leaving target processor paused

In another shell I left the nios2-terminal running, without any reaction.

Screening through the addresses, finally verification worked out - or at least it seemed to - at all adresses between 0xc8000000 and 0xc8040fff. Why??!!

I may nios2-elf-objcopy the u-boot to a u-boot.srec and run nios2-gdb-server on it. Bt shows me the "start()", any "step", "next" or "continue" does not show anything further. Interesting, at 0xc8040fff in particular some of my leds light up, nios2-terminal prints '4', but that's it.

Why this address? Is this really a progress, or just a weird coincidence. How to get the correct address of the RESET to jump in? Or what do I need to provide at U-boot's CONFIG_SYS_MONITOR_BASE exactly for booting into a nios 2?

Why or what do I anyway have to set here? Ain't the addresses actually already known by the DTS? Is this just a layout for how to use the SDRAM? So, but why do I need to figure out a specific RESET address? I'm confused.