Two NIOS2 sharing the same SDRAM for instruction/data master

I designed a similar 2 CPU / 1 SDRAM system (not Nios) a few years ago.

So, you can surely design a system with two Nios processors and a single shared sdram device, but you must be aware of these points:

- sdram accesses will be shared between the two processors, so the running applications could suffer great performance decrement; the actual performance will depend on several factors, i.e. number of sdram accesses, arbitration priorities and cache usage.

- you must carefully instruct the linker to place memory sections into proper sdram areas in order to avoid overlapping and consequent data/code corruption.

I think the first point is the major issure. I'd suggest you keep the more program code you can in onchip memory, along with stack and often-accessed data.

Move into sdram only non time-critical parts and bulk data or seldom accessed data.