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Honored Contributor
Honored ContributorTSE with SGDMA Busy problem
I have a system with 2 CPUs. I have a working system where I have connected up a TSE to 2 seperate SGDMAs (Rx & Tx) and 2 seperate memories (Rx & Tx) which is controlled by the first CPU. We ...
Altera_ForumHonored Contributor
Honored ContributorThings are a little different. We renamed the DMA related components (TSE, SGDMA. memory associated with DMA) within our SOPC system.
Now when start a DMA and read back the DMA status we get an 0x18. That is BUSY + CHAIN_COMPLETED. The 0x85 in the descriptor control byte is still there. When DMA works , the 0x10 in the DMA status turns into a 0xC (DESCRIPTOR_COMPLETED + CHAIN_COMPLETED. It should be impossible to get a CHAIN_COMPLETED without an accompanying DECRIPTOR_COMPLETED or to get a CHAIN_COMPLETED without clearing the busy or the descriptor control byte but we're managing both.
