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Altera_Forum
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14 years ago

TSE with SGDMA Busy problem

I have a system with 2 CPUs. I have a working system where I have connected up a TSE to 2 seperate SGDMAs (Rx & Tx) and 2 seperate memories (Rx & Tx) which is controlled by the first CPU. We ...
Altera_Forum's avatar
Altera_Forum
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14 years ago

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The Run BIT is still set -we still read a value of 0x85 from the Control Field inside the Descriptor.

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This means the descriptor has the OWNED_BY_HW bit set (0x80).

I think the last descriptor in your chain must have its OWNED_BY_HW bit cleared.

Otherwise the dma core is supposed to continue processing and would not release the busy flag.

Are you using a true descriptor chain or are you testing with a single one? If the latter, then the error is indeed on sw side (LOL :cool:) because OWNED_BY_HW should have been programmed to zero. If instead the transfer stops on the very first descriptor of the chain, then it's likely 'you' have a problem :oops: