Altera_Forum
Honored Contributor
19 years agotrouble with the optimizing level settings
Hi all,
I am having trouble with the optimizing level settings of my design which uses Nios II embedded system as a camera controller and transfering bulk image data to PC by UDP. Now the fastest speed I ever got is about 9Mbit/s ( 1.1MByte/s) but that is far from satisfactory. So I am trying to apply the compiler optimization options to improve the performance. The problem is that whenever I use any compiler optimize level other than -O0, the entire system stops functioning and no data is transferred at all. It must be compiled with -O0 level in order to work. My testing environment is Cyclone 1c20 FPGA chip on a custom borad (which is very similar to the Nios II evaluation board), 50MHz Nios II/f cpu, Lan91c111 MAC. I am using lwIP 1.1 and uC/OS II and the project was biuld with Quartus II 6.0 and Nios IDE 6.0 software. Does anybody have any idea about this problem? Thank you!! Mason