Forum Discussion
Deshi_Intel
Regular Contributor
7 years agoHi Leon,
It seems like you are trying to bring up TSE IP by referencing to certain example design but it's not working.
May I know which FPGA that you are using and which example design that you refer to ?
Just to confirm you are running simulation and not hardware testing right ?
Have you tried to verify the example design instead of your own design ? Then you can compare the difference and it may lead to the actual root cause.
Thanks.
Regards,
dlim