Tightly Coupled Memory

To re-iterate, if your code/data is going to be in internal fpga memory then, if possible, make the nios access it as tightly coupled code/data. That will give you faster accesses and use less fpga resource.

You will probably still need the instruction cache for the boot code (for boot from flash or jtag) - but you can make it minimally sized.

The code I've written is very performance critical - 'hard real time'. I had to ensure the worst-case code paths didn't exceed the available clock count.