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Altera_Forum
Honored Contributor
16 years agoThe problem of interrupt
hello!
I am learning how to edit a component,but there are two errors that I cann't solve,can anyone suggest me? http://b32.photo.store.qq.com/http_imgload.cgi?/rurl4_b=b579f8b54f494fc69149a5de70a1aee97ae940bc75e456f68f02470592f5952d5058f6e366fb6918e7ccbf21ef48868f0212d77e18b3522b325715a7e1b185c098ba27d40c5804c65905e1cda0092f7025180e37&a=28&b=32 the code is: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity inter is port(clk: in std_logic; reset_n: in std_logic; chipselect: in std_logic; address: in std_logic; write_n: in std_logic; writedata: in std_logic_vector(31 downto 0); read_n: in std_logic; readdata: out std_logic_vector(31 downto 0); irq: out std_logic); end inter; architecture behave of inter is signal status:std_logic_vector(31 downto 0); signal control:std_logic_vector(31 downto 0); signal counter:std_logic_vector(23 downto 0); signal sign:std_logic; begin process(reset_n,chipselect,write_n,read_n,writedata) begin if(reset_n='0')then status<=(others=>'0'); control<=(others=>'0'); sign<='0'; elsif(chipselect='0')then if(write_n='0')then case address is when '0'=>status<=writedata; when '1'=>control<=writedata; end case; end if; if(read_n='0')then case address is when '0'=>readdata<=status; when '1'=>readdata<=control; end case; end if; end if; end process; process(clk,chipselect,write_n) begin if(clk'event and clk='1')then if(chipselect='0' and write_n='1' and control(0)='1' and status(0)='0')then counter<=counter+1; if(counter>"111111111111111111110000")then sign<='1'; status<="000000000000000000000001"; else sign<='0'; end if; end if; end if; end process; irq<=sign; end behave; thank you very much!2 Replies
- Altera_Forum
Honored Contributor
What problem do you have?
All the images that you send on this forum are unreadable. You should find another provider for them, or attach them to your message. - Altera_Forum
Honored Contributor
I have resolve the question,thank you all the same!