Strange Problems with SOPC6.0 I have never seen

I wanna add an accumulator on my board with standard NIOS2 kits.

First,I use megawizard to make a accumulator file acc.v.

Second,writing a file avalon_acc.v to work with acc.v.

But when I add a user-defined component and add the avalon_acc.v as the top

module,the errors appeared：

Error: command "quartus_map --generate_hdl_interface=E:/DATA/altera_experiment/Quartus6.0/test2_ACC/ce_temp_directory/avalon_acc.v ce_temp_directory/ce_temp_quartus_project" returned 3

Error (10149): Verilog HDL Declaration error at avalon_acc.v(46): identifier "acc_in" is already declared in the present scope File: E:/DATA/altera_experiment/Quartus6.0/test2_ACC/ce_temp_directory/avalon_acc.v Line: 46

Error (10149): Verilog HDL Declaration error at avalon_acc.v(47): identifier "acc_reset" is already declared in the present scope File: E:/DATA/altera_experiment/Quartus6.0/test2_ACC/ce_temp_directory/avalon_acc.v Line: 47

Error (10280): Verilog HDL Port Declaration error at avalon_acc.v(49): cannot redeclare port "read_data" because it is already fully declared File: E:/DATA/altera_experiment/Quartus6.0/test2_ACC/ce_temp_directory/avalon_acc.v Line: 49

Error (10112): Ignored module "avalon_acc" at avalon_acc.v(2) due to previous errors File:

E:/DATA/altera_experiment/Quartus6.0/test2_ACC/ce_temp_directory/avalon_acc.v Line: 2

Error: Quartus II Analysis & Synthesis was unsuccessful. 4 errors, 0 warnings

Error: Processing ended: Sat Aug 05 00:19:29 2006

Error: Elapsed time: 00:00:00

Error: E:/DATA/altera_experiment/Quartus6.0/test2_ACC/ce_temp_directory/avalon_acc.v.xml does not exist

These problems didn't appear when I use Quartus2 5.0,can someone help me?

I am a newer~ http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/unsure.gif