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Altera_Forum
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19 years ago

SRAM interface on UP3

I am developing vhdl file to interface SRAM on UP3 kit with avalon tri state bridge. I know SLS has SRAM interface available, but I want to develop my own. I have signals address, data, write_n, outp...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
19 years ago

There are (or used to be) instructions on how to build your own SRAM "component" in the SOPC Builder memory chapter of the QII handbook.

Alternately, you could take a look at either Altera's component or SLS's and reverse engineer from there. Altera's version is written in Europa (Perl-based HDL generation), but we're not talking about a complex component here, so it's not difficult to understand.

An SRAM interface is arguably the easiest thing to design in Avalon. You're just passing these signals through to the tristate bus and then connecting them to your SRAM in the top-level design of your FPGA. No HDL (of your own) should be required. You should just be telling the switch fabric how to connect to your SRAM and what sort of wait states/cycles to apply.

You mentioned that you tied byteenable low. This is not correct. There should be byteenable pins on your SRAM and these should be connected there. In your case, byteenable should be 2 bits wide.

Ok...that should get you started.

Best Regards,

- slacker