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Honored Contributor
Honored ContributorSPI Slave bug?
Has anybody used the SPI core as a slave device in a NIOS II implementation? If so, have you had relatively frequent data errors? There is no HAL for the SPI as slave, so I'm just using th...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- SOPC bilder generates, as seems, wrong verilog code for SPI slave, at SS_n rise edge rx register shifted one more time, and ROE bit is set to 1. To avoid this, you should read RX register before SS_n rise edge or delay SS_n edge, if it possible. --- Quote End --- Could you elaborate on this? Also, is Altera going to fix this bug?
