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I changed the waiting completion loop like you told me and it doesn't work. I also tried instead to wait on the TRDY-Flag to wait on the RRDY-Flag because how far I understand if the RRDY-Flag is "1" it is possible to read the register. But it also doesn't work.
I`m also checked the setup in QSYS of the both SPI Cores and till the difference that one is a master and the other one is a slave they have the same setting in relation to the clock polarity and phase. So may I change the setting for the slave or the master? Or what can I do farther?
Thanks in advance for your help!
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