Some questions about Arria 10 PCI Express HIP and topologies

Hello,

I'm working on a project using several Intel/Altera FPGA Arria 10 and PCI Express protocol.

At this stage, I would like to provide a communication between two FPGAs Arria 10, one configured as a Root-port or Root-complex device and the other one as a End-point device.

I tried to understand the PCI Express standar from PCISIG and the Arria 10 PCI Express HIP datasheet from Intel/Altera but its still difficult for me.

I will need someone more exprimented than me to explain and dis-blurring several aspects of these documents especially about the use of the PCI Express HIP.

I would like to know too if using its two FPGAs as describe upper is possible without using a CPU (I thought to use the Arria 10 embedded CPU to use the PCI protocol) and if this one can be replace by a VHDL architecture like a bug state machine.

Thanks to you,

Cotton