Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorSoc simulation in VHDL
Hello all, I am trying to simulation a Qsys system that contains an HPS but I get the following error in Modelsim : Fatal: (vsim-3362) The type of VHDL port 'clk' is invalid for Verilog co...
Altera_ForumHonored Contributor
Honored ContributorWithout seeing the code, I cant see what the problem is.
But I do know most Altera IP is generated in Verilog/SV, with VHDL wrappers (if they even bother to provide one). There could be some error in the code generation somewhere that may need a ticket raising.
