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Altera_Forum
Honored Contributor
Honored ContributorSoC FPGA Ethernet Performance
Hi, I have application that needs to transfer 1 gigabit/s of data generated by the FPGA over Ethernet. FPGA generated data would be written to HPS's DDR3-memory. The data would be transferred o...
Altera_ForumHonored Contributor
Honored ContributorWhere does this 500 Mbps limitation comes from? From the memory controller's bandwidth, processor's speed or L3 Interconnect's limited bandwidth? If the limiting factor is some of these, I would not expect to get 1 gigabit performance with 2 ethernet ports.
