Slow DDR access.

Hi Guys,

We are using Nios II with a DDR HP Controller in full-rate, both at 100MHz on Cyclone III. The design is an SOPC builder with Avalon-MM interface. Our DDR Memory is a single device 16bit Micron MT46V32M16-6. The DDR accesses work fine but slower than expected. According to the DDR Controller Table 4-2 the typical latency should be 10 clocks (=100nsec) for Write and 20 clocks (=200nsec) for Read, while we get 240nsec for Writes and 500nsec for Reads. Our parameters definitions are attached in files "DDR Memory Parameters1/2.pdf". Somebody has improvement suggestions?? We are already thankful.

Thanks and Bye,

ShmuelD