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Altera_Forum's avatar
Altera_Forum
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15 years ago

Slow DDR access.

Hi Guys, We are using Nios II with a DDR HP Controller in full-rate, both at 100MHz on Cyclone III. The design is an SOPC builder with Avalon-MM interface. Our DDR Memory is a single device 16b...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Another issue that can't help fmax is the way the Avalon MM bus seems to do address decoding.

AFAICT it never aliases targets - so will be doing comparisons on more bits that strictly necessary. The nios selecting between tightly coupled data and other data ought to generate warnings for some cases it just allows.

We have a system with a 16MB sdram (base address 16M), some 16kB (or smaller) M9K blocks (below 128kB) and some io (just above 128kb).

The address decode need only use A24 (to select SDRAM) A17 (for io) and A14-16 to select between the M9K blocks.

However I don't see any address aliasing - even if we put down a 12kB block of M9K. All these extra comparisons must be affecting fmax.

(and there doesn't even seem to be a 'normal' option to enable an interrupt if the nios accessed an unmapped slave address.