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Altera_Forum
Honored Contributor
Honored ContributorSlow DDR access.
Hi Guys, We are using Nios II with a DDR HP Controller in full-rate, both at 100MHz on Cyclone III. The design is an SOPC builder with Avalon-MM interface. Our DDR Memory is a single device 16b...
Altera_ForumHonored Contributor
Honored ContributorI agree. I recently gave a presentation to Altera in which I mentioned they should at least make the user aware of the fact that they are inserting clock crossing adapters and such. I think SoPC builder could benefit from "Design Advisors" that help the user understand what SoPC builder is doing and make recommendations on how to say reduce logic or increase fmax.
Now in reality if you know what you're looking for you will notice the adapters being inserted as they are called out during generation and of course they show up in your Quartus project. The input clock to the SDRAM should be your regular sysclk. However, everything that interfaces to the SDRAM should use the PLL output from the SDRAM (your DDR_Controller_sysclk). Jake
