Simple Nios II DK programming question

Hi Nails;

Thanks for the response.

I found the problem, pretty simple as you suspected.

It turns out that on this DK board there is an output pin from the FPGA which is connected to the CPLD which handles configuration. When this FPGA output goes low, it causes the board to be reset.

I hadn't bothered to assign anything to this pin, so it was tri-stated. The CPLD must have seen this as a low and immediately caused the board to reset.

Once I realized that this pin existed, it was easy enough to force it high. Now things are working as expected.

Rgds,

Steve