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Altera_Forum's avatar
Altera_Forum
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15 years ago

signed division

Hi all,

I design a piece of hardware using simple division as shown in below:

module divider (in1, in2, division, multiply);

//parameter

parameter DATA_WIDTH = 32;

//Input

input [DATA_WIDTH-1:0] in1;

input [DATA_WIDTH-1:0] in2;

//Output

output [DATA_WIDTH-1:0] division;

output [DATA_WIDTH-1:0] multiply;

assign division = (in1/in2);

assign multiply = in1*in2;

endmodule

It works fine with positive number, however when I try with

in1=-2352,

in2=-588,

by right, (-2352/-588) = 2, i should get 2. But the simulation result gives me 0 instead.

Besides, when I try with one of the input is positive number,

in1=2352,

in2=-588,

by right, (2352/-588) = -2, i should get -2. But the simulation result gives me 0 instead.

What is going wrong and how to overcome this problem?

thanks in advance,

regards,

ty6

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    I can't see a signed type definition in your code. By Verilog specification, you're performing unsigned arithmetic, which would pretty explain the issue.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    I'm quite new to verilog, could you please explain what is signed type definition?

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    alright, I google the signed type definition and I modify my code from

    input [DATA_WIDTH-1:0] in1 ==> input signed [DATA_WIDTH-1:0] in1;

    Thank you FVM.

    The next question is : is this signed type definition synthesizable?