SGDMA debug

Well, I've changed the source to populate 32bit data. E.g. all pointers use 32bit allocation - check create_test_data(), however I am not sure if I am doing it correctly. In the validate part, I am reading the data using iord_32direct() instead of iord_8direct().

You can check the current source ->here<- (http://www.codeupload.com/4061).

Test data creation is between lines 131-155 and I am reading the memory in lines 205-206. Maybe I need to use a higher offset when reading with iord_32direct() instead of iord_8direct?

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EDIT:

right, so I suppose the problem was 8bit read/write instead of moving the cycle every 4 bytes to work with 32bit data and iord_32direct().

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Now my task is to get 32bit packets from my packet source (I have Avalon-ST component, which takes packet data from logic and moves to Avalon-ST) and place it in Nios. I suppose I should use SGDMA stream-to-memory, then read the data using iord_direct32() in Nios. I will fill the TSE buffer in function ip_send() with that data and send it over ethernet.

If I understart correctly, I need to do sync transfer in SGDMA, because my component generates packet start and packet stop signals. Maybe there is an example of such thing, when only Avalon-ST source and SGDMA RX are used?

P.S. The data is video stream, I have to use something faster than simple DMA + I want to learn to use SGDMA, since I will have to receive the same data on the other end and parse it back to logic.