set_output_delay explained for dummies

Ah okay. Your post has made me realize that I was thinking the data would arrive too early (and maybe/maybe-not going invalid before 3.0 ns) while I think you were implying it would probably arrive too late to meet the 1.0 ns requirement.

In super general concepts: The FPGA data output is going to have its own output-valid window relative to that register's clock. I need to do whatever it takes to make sure the output valid window overlaps the downstream's devices input valid window (delay either clock or data, as appropriate). I should account for PCB delays and length-mismatches as well.