set_output_delay explained for dummies

The ideal clock occurs at both the FPGA and the external device at times 0ns, 10ns, etc. If the FPGA needs to get its data out within 1ns, then making the clock delay to the external device longer would help with this setup, but the clock delay to the external device is outside the FPGA, i.e. the FPGA fit can't affect that. The only things the FPGA can affect are the clock coming into the FPGA to the output register(launch clock path) and the delay from the register to the output port(data path). These two things make up the Data Arrival Path, and we essentially want them to be less than 1ns.

I recommend not spending a lot of time on hypotheticals and instead figure out your specific timing case. There are all sorts of ways you can confuse yourself with hypotheticals that are not worth the time.