set_output_delay explained for dummies

The example was fake and exaggerated, just for me to get the basic understanding, +/- convention down. So now that I know how to constrain an output valid window, I want to address a different part of your post: "so if you go with this you won't be able to close timing." I thought the constraint simply defines timing relative to a clock: For example, if I generate a clock on an output port and send it to the receiving device, the timing tools will check if the output data can meet timing relative to my output clock. How I actually implement the design could be different, right? Maybe I use a PLL to generate a synchronous clock with a phase offset and use that as the output clock port, but the data is still being clocked out with a different phase. This is doable, correct? And the tools should be able to interpret my circuits and still tell me that the output pin timing is met?