set_output_delay explained for dummies

Yes, in my example the data can be invalid between times 1-7ns(and is valid between times 7-11ns, where the latch edge is at 10). You need it valid between times 1-3ns. That's kind of a strange requirement, but nothing wrong with it. There are a couple ways to do this. Let's start with what you wrote, so data must be valid between 1-3ns, i.e. you're latching between 1-3ns. Then you would have:

set_output_delay -max 9

set_output_delay -min 7

So the data must get out of the FPGA and valid within 1ns. For hold, we're saying the data being launched can't corrupt the previous latch edge, which could be as high at time -7ns, so the min delay is +7ns. By having a positive 7ns delay, your Tco could be -7ns and still meet timing. Of course, that physically can't happen. I strongly recommend drawing a waveform with the launch clock, another with the latch clock, and then draw squares to show where the data is valid(e.g. -9to-7, 1to3, 11to13,etc.) and then everything in between is invalid. One quick test I do is that 9-7=2ns, so the data must be valid for at least 2ns.

So that is probably not possible to do in hardware. When you launch data at time 0ns, your 10ns latch edge is better off grabbing the valid data at times 11-13. So for that you could subtract 10ns from everything:

set_output_delay -max -1

set_output_delay -min -3

Now your data must get out later than time 3ns but no longer than time 11ns. That should be pretty easy to do. (I have no idea what your clock period is, so if it's not 10ns then how easy or not easy this is could change)