Searching example code or manual entry regarding ACP mapping for EMAC DMA access

Hello,

we are using a Cyclone V SOC and its integrated EMAC for a high bandwidth application.

• All communication to the device are based on gigabit ethernet.

• The mass-data are processed mostly by FPGA hardware

• The control channel is done by SW

The EMAC should now

• Send mass-data from one part of the DDR3 without usage of the l2 cache

• ​... so the bandwidth of the cache isn't affected by this

• Send sw generated control packets from the other part of the DDR3 with the usage of the l2 cache

• ... so our IP-Stack can stay unaware about caching effects etc.

We thought, this should be possible using a well-tailored ACP window so the EMAC can differentiate between the two DDR3 locations.

For now, we have only found the register description

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-v/cv_5v4.pdf (starting at page 600).and would be happy to find a more step-by-step description ... ACP for Dummies ... more or less.

=> Is there an easy way to get a system running without too much headaches?

.... I'm doing direct register writes quite often (coming from the FPGA-side) - I would just like to exploit any possibilities for a more high-level-approach ;-)

Best regards,

Roman

PS: I didn't find a subforum where the question might have fitted any better but please move me away if you like to