SDRAM verify failed in NIOS II IDE

Yes, I have use PLL to compensate the phase shift.

I use Mtx Cyclone Board. I have read the DataSheet of the board. The sheet says

"The clock driving the SDRAM is based on the 32.768MHz on-board oscillator (no multiply or divide), and is delayed by 27ns before being sent to the SDRAM component. This allows a 3-4 ns delay for the SDRAM clock to arrive at the chip, which in turn allows the SDRAM access to occupy the entire 30.5 ns clock period if needed."

The Phase shift is 318.51 in 32.768MHz.

I use PLL to generate the 49.152MHz Clock, the 1.5 times board clock. So I set 18ns in the clock phase shiht tab. But IDE displayed verify failed.