SDRAM verify failed in NIOS II IDE

The nios core and SDRAM peripheral operates (samples) on rising clock edges. SDRAM clocks out data on rising edges (valid on falling edges). If you do not run the SDRAM clock through a PLL to tweak phase shifting, it will not work. If your SDRAM is very close to the FPGA, you can get away with using an inverter (180 degrees). I have done that up to 96 MHz. If you have more than 2cm of distance between the SDRAM and FPGA, you will have to use the PLL and tweak the clock using an oscilloscope. Have you tried using the FS2 console to modify SDRAM contents?