sdram use different clk with other ip in nios

If your sdram controller exposes a MM slave interface, there's no difference between sdram or any other type of memory. From Nios point of view (or any other MM bus master), sdram is equivalent to onchip ram, flash memory, sram or whatever. Clearly you'll have different access times, but you usually don't bother it at the Nios code level.

Placing both code and data in sdram is indeed the common practice.

You can have N memory devices connected to Nios and you can distribute code/data sections across them.

For example you map generic code and data to sdram, but you can move time critical functions to faster onchip ram to optimize performance. You can remap whole code sections by adjusting linker settings.

You can also remap a single function or variable by using the attribute directive:

__attribute__ ((section (<memory device name>)));

Regarding the possibility of sharing sdram among different ip, the answer is still Yes.

The typical situation is when you have Nios processor and one or more DMA devices connected to sdram (or, in general, to the data bus). Both are MM masters and they can independently read/write the same memory device.

Bus arbitration is managed automatically by the Avalon bus fabric; you only have to worry about the consistency of the r/w operations (i.e. the dma write must not corrupt Nios code, but it should write in the assigned memory area which is supposed to store data).

This also applies when you have multiple Nios processors and a single sdram memory: each processor would run code from a specific sdram address range and they could possibly share a common address range for exchanging some data.

Browse the Nios and sopc information for extended info and examples:

http://www.altera.com/literature/lit-nio2.jsp#related_documentation