SDRAM signals managing

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I have three new questions:

1-How to make the SDRAM available both for the software part (a Nios II cpu in a Qsys system) and the hardware part (a Quartus II design)?

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The hardware that needs to access the SDRAM needs to be written as an Avalon-MM master, so that it can initiate SDRAM reads or writes.

Alternatively, your hardware can be an Avalon-MM slave or Avalon-ST sink/source, and you can use a DMA controller to move data from your component to/from SDRAM.

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2-How to tell Qsys that the program of the cpu should be stored in the internal FPGA memory and the data should be stored in the SDRAM?

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That is not a Qsys task. That is the job of the linker script.

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3-I've downloaded this file: http://www.altera.com/products/ip/altera/ocore_sdr_sdram.html

and a first problem is the address bus width. In the file it's 12-bit but in the first qsys system it was 13-bit.

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You already have a working SDRAM controller (using the standard Altera Avalon-MM SDRAM controller), why are you trying to use this design?

Cheers,

Dave